In conventional FinFETs, the horizontal channel is positioned on a vertical sidewall within the fin. Flash cell floating gate (FG) and control gate (CG) need to be positioned at the sides of the fin. The flash cell total gate height is higher than the logic gate and leads to processing challenges. In particular, a higher FG height than the logic metal gate leads to challenges with metal gate chemical mechanical planarization (CMP), especially for gate-last replacement metal gate (RMG) processing.
A need therefore exists for methodology enabling elimination of the step-height difference of flash and logic gates and the related device.